使用Yosys，免费和开源的超棒 HDL 合成工具箱，具有额外的酷（和免费）（并且比当前的 Vivado 更快）（我在演讲和啤酒中提到过免费吗？）（太棒了）！

获取 yosys、xdot 实用程序（通常是名为 python-xdot 的包的一部分）以及 graphviz。

然后，在 verilog 文件中执行类似操作（我们称之为minifsm.v）：

module piggybank (
                  input         clk,
                  input         reset,
                  input [8:0]   deposit,
                  input [8:0]   withdrawal,
                  output [16:0] balance,
                  output        success
                  );
   reg [16:0]                   _balance;
   assign balance = _balance;
   wire [8:0]                   interest = _balance [16:9];
   reg [5:0]                    time_o_clock;
   localparam STATE_OPEN = 0;
   localparam STATE_CLOSED = 1;
   reg                          openness;
   assign success = (deposit == 0 && withdrawal == 0) || (openness == STATE_OPEN && (withdrawal <= _balance));
   always @(posedge clk)
     if(reset) begin
        _balance <= 0;
        openness <= STATE_CLOSED;
        time_o_clock <= 0;
     end else begin
        if (openness == STATE_CLOSED) begin
           if(time_o_clock == 5'd7) begin
              openness <= STATE_OPEN;
              time_o_clock <= 0;
           end else begin
              time_o_clock <= time_o_clock + 1;
           end
           if (time_o_clock == 0) begin //add interest at closing
              _balance <= _balance + interest;
           end;
        end else begin //We're open!
           if(time_o_clock == 5'd9) begin // open for 9h
              openness <= STATE_CLOSED;
              time_o_clock <= 0;
           end else begin
              _balance <= (success) ? _balance + deposit - withdrawal : _balance;
              time_o_clock <= time_o_clock + 1;
           end
        end // else: !if(openness == STATE_CLOSED)
     end // else: !if(reset)
endmodule // piggybank

并运行 yosys：

yosys

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2016  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.6+155 (git sha1 a72fb85, clang 3.7.0 -fPIC -Os)

加载 verilog 文件，然后检查层次结构，然后提取进程、优化、查找状态机、优化并显示图形：

yosys> read_verilog minifsm.v
… …
yosys> hierarchy -check;
yosys> proc;
yosys> opt;
yosys> fsm;
yosys> opt;
yosys> show;

你会得到类似的东西

使用show命令的不同选项，您也可以将图形保存到文件中。Yosys 允许您在 verilog、EDIF、BLIF 等中编写“扁平化”逻辑，为特定技术平台（包括 ArachnePnR 支持的平台）综合和映射，并做更多有趣的事情。本质上，Yosys 就像让知道如何构建编译器的人编写一个 Verilog 合成器。

你有什么？这些具有该功能，具有各种输出质量。

• 综合性
• Synopsys 设计编译器
• Altera Quartus II
• 赛灵思 ISE

Altera Quartus 应该可以做到。

当我在学习 VHDL 时，我有时会使用 Quartus Web Edition 进行反向转换（从原理图开始获得等效的 VHDL），并且它有效。